Semiconductor devices usually include a large number of features or components—such as transistors, switches and conductive lines—built on an underlying substrate or wafer. The components are usually built by successively depositing layers of different materials on the substrate and then etching and/or selectively removing all or part of the deposited layers. The deposited layers are of different materials depending on the component, but can include metals, metal alloys, pure semiconductors, doped semiconductors, and dielectrics.
Certain semiconductor devices include a variety of conducting paths or interconnects between components of the device. These interconnects are often built by etching a feature such as a trench into a dielectric layer, and then depositing an adhesion layer, a barrier layer and, finally a conductive layer onto the dielectric layer. To complete the interconnect, the conductive layer, barrier layer and adhesion layer must be removed from the regions of the dielectric layer surrounding the feature (also known as the “field”), leaving the trench filled with a conductive layer, usually metal, separated from the dielectric layer by the barrier layer and the adhesion layer.
The method of choice for removing conductive and barrier layers from a semiconductor wafer has been chemical mechanical polishing (CMP). In CMP, a mildly abrasive slurry is poured onto a polishing pad, and the wafer surface is then pressed onto the slurry with a force calculated to exert a certain pressure on the surface of the wafer. The polishing pad and the surface of the wafer move against each other causing the abrasive slurry to grind away the conductive or barrier layers on the surface of the wafer. Despite its prevalence, however, CMP has some important disadvantages. CMP is inherently expensive because it uses substantial amounts of consumables that cannot be re-used, such as polishing pads and abrasive slurry. Because CMP involves polishing the surface of a wafer by the exertion of a mechanical shear stress on the surface of the wafer, CMP can easily damage structures on the wafer. When metal and barrier layers are used on a wafer to form a structure in a dielectric material with a low dielectric constant (also known as a low-k dielectric), CMP has the potential for large amounts of damage. Low-k dielectrics have correspondingly low material properties, such as Young's modulus, hardness, toughness, etc, meaning that mechanical stresses can be particularly damaging. Since damage to even a small number of structures on a wafer can render the entire wafer useless, use of CMP, particularly with low-k dielectrics, can substantially lower the yield and raise the expense.
There have been attempts to use a hybrid method that combines CMP with electrochemical removal of layers from a wafer, but these attempts have not had satisfactory results. Because the hybrid method continues to rely on mechanical forces, it carries with it all the disadvantages of CMP methods. When metal and barrier layers are used on a wafer to form a structure in a dielectric material, electrochemical removal has yielded poor results. Traditional barrier materials are very resistant, meaning that they require very high applied potentials for removal. Moreover, traditional barrier materials have been difficult to remove without also removing the metal layer; in other words, existing electrochemical approaches are not selective enough to the barrier materials used.